1. Technical Field
The present disclosure is generally related to electronic devices, and, more particularly, is related to thermal resistance estimation in field effect transistor structures.
2. Description of the Related Art
The reliability and performance of field effect transistors (FETs) and monolithic microwave integrated circuits (MMICs), particularly for power devices, depend critically on the operating channel temperature. For instance, the reliability and power performance of gallium nitride (GaN) devices depend critically on the operating channel (or junction) temperature. Power densities of up to 30 watts per millimeter (W/mm) have been obtained, usually from single (or double) finger (gate) devices, which typically run cooler than multi-finger devices (where lower power densities are generally observed for multi-finger devices). Lower power densities for multi-finger devices are mainly due to thermal effects. The device performance is thus critically affected by self-heating. The maximum allowed channel temperature largely drives the design of the cooling system, device package, and maximum direct current/radio frequency (direct current/radio frequency (DC/RF)) power limitations. Therefore, an accurate estimate of channel temperature is highly desirable during the device (or circuit) design phase.
Generally, the temperature behavior can be described using a three-dimensional Laplace equation defined as follows in equation (1):∇2T(x,y,z)=0,  (1)where T(x, y, z) is the temperature at any point in space. For devices with some geometric configurations, such as concentric spheres, concentric cylinders, or parallel plates, Laplace's equation can be solved analytically in closed form. But for most geometric configurations, the solution for Laplace's equation is either intractable or results in infinite series summations. Hence, numerical solutions are more commonly pursued, and a number of simulators have been developed based on finite volume, finite difference, and finite element techniques.
However, solving Laplace's equation using numerical methods may not be practical for many circuit designers. For instance, solving Laplace's equation using numerical methods may require great effort (and time) to define the problem and the boundary conditions, and frequently, the solution does not converge. Also, solving Laplace's equation using numerical methods does not allow for interactive optimization of the device configuration with regard to thermal resistance during MMIC designs. Further, the software (e.g., simulators) to implement numerical methods is generally expensive and often unavailable to an MMIC designer.
For these reasons, among others, many designers rely on simplified models or formulas to estimate the channel temperature. Simplified models relate the device geometrical structure to the thermal resistance and are relatively easy to understand and apply. One drawback of using these simplified models is the inaccuracy of the result. A classical and popular method for calculating thermal resistance of a FET is an approximation based on Fourier's conduction law. This approach makes the assumption that heat transfer is confined to a 45 degree wedge of material between the gate and the base. The resulting equation (2) can be shown as follows:
                              θ          =                      t                                          k                ⁡                                  (                                                            W                      g                                        +                    t                                    )                                            ⁢                              (                                                      L                    g                                    +                  t                                )                                                    ,                            (        2        )            where t is the substrate thickness, k is the thermal conductivity, Wg is a gate width and Lg is a gate length. Although appreciated for its simplicity and ease of use, it has been shown to lack accuracy. Several modifications have been proposed to the formula above to improve its accuracy for different special cases (e.g., square, circular disk, etc.). However, the accuracy of the simple models, when applied to FET problems, remains an issue (percentage error±10-50%) because the heat source is a thin long line, not a circle or a square.
An analytical solution for a rectangular patch on a substrate and a circular patch on a cylinder is available in the form of an infinite series summation. The exact solution is the sum of three infinite series with the last term consisting of two nested infinite summations. After using the infinite series solution for a few cases, one quickly realizes that convergence is very slow with tens of thousands of terms required to arrive at a reasonable answer, assuming numerical instabilities and errors are kept under control.
Finally, earlier closed form expressions based on transmission line analogies have yielded results with 10-20% error.